The present invention relates to technology of timing verification of an LSI designed on the cell level, and more particularly to a method of calculating an after-deterioration delay change of each of the cells of the LSI in order to estimate deterioration in reliability of the LSI due to the influence of hot carriers.
In designing and production of LSIs, the progress of the semiconductor process technology brings an achievement of the miniaturization of elements using a design rule of less than 0.5 .mu.m which is called deep submicron. In recent years, as called a "system-on-silicon age", there has started development of an LSI chip highly integrated such that a whole system can be mounted on a single chip.
On the other hand, there are instances where the miniaturization of transistor elements causes trouble in view of reliability in operation of the LSI. Accordingly, when the minimum machining sizes are of the order of submicron, it becomes necessary to consider, in designing an LSI chip, even the physical phenomena of a semiconductor. Of these, deterioration in reliability due to the influence of hot carriers is one of the greatest problems.
The following description will discuss briefly the delay degradation due to hot carriers. In a channel of a MOSFET, the electric field E is simply expressed as follows: EQU E=Vds/Leff
wherein Vds is the voltage across the drain and the source, and Leff is the effective channel length. In fact, the electric field E in the channel is concentrated in the depletion layer region in the vicinity of the drain. Accordingly, its maximum value is much higher than the value obtained using the formula above-mentioned.
When the effective channel length Leff is shortened due to the miniaturization of an MOSFET, the electric field E is not increased, as apparent from the above formula, if the voltage Vds across the drain and the source is reduced in proportion to the effective channel length Leff. However, the condition of reduction in Vds in proportion to the Leff is actually not satisfied and the channel electric field E is increased with the development of miniaturization.
When an element is miniaturized, the product of the channel length and the hot electron critical electric field gets near to the operational voltage of the transistor if the power voltage undergoes no change. Accordingly, a sufficient energy is given to electrons, which may enter into the gate oxide layer across the energy barrier at the boundary. Entering electrons are trapped and accumulated to increase the threshold voltage Vth in a short time. The transistor electric current is proportional to (Vgs-Vth).sup.2 in which Vgs is the voltage across the gate and the source. The increase in threshold voltage Vth causes the mutual conductance and the current drive ability to be deteriorated.
Such deterioration in threshold Vth due to hot electrons is generated with the passage of time. More specifically, the deterioration proceeds and the operational speed is lowered with an increase in the accumulation period of time during which the transistor operates.
To retard the deterioration, the power voltage may be lowered to lower the electric field E in the channel. However, the effective channel length Leff is shortened due to miniaturization. Therefore, even though the power voltage is lowered, it cannot always be known whether or not the channel electric field E is lowered. When the electric current flowing in the transistor is reduced in amount, the deterioration can be retarded. However, this is not preferable because the transistor drive ability is lowered.
Conventionally, the estimation of deterioration in reliability due to the influence of hot carriers has been made on the level of a transistor. For example, there are available a method in which a hot carrier deterioration model is incorporated in a circuit simulator for finding each deteriorated transistor (Japanese Patent Laid-Open Publication No. 1-94484), and a method in which the stress dependency of each exponent in the formula of deterioration rate is obtained and the hot carrier deterioration under the AC stress is simulated (Japanese Patent Laid-Open Publication No. 7-99302).
To assure the reliability of an LSI in connection with changes thereof with the passage of time, the timing verification of the LSI has conventionally been made based on the result of estimation on the deterioration of each single transistor itself due to hot carriers. In such a case, to assure the reliability of the LSI, the greatest expected number of times has generally been used as the number of operation times of the transistor.
In fact, however, the degree of deterioration in reliability varies with the total operation period of time of each transistor as mentioned earlier, and it cannot be considered that all the transistors forming an LSI operate for the same period of time. That is, according to each of the conventional methods, the guarantee on reliability is liable to be excessive.
The reliability is guaranteed with the worst case taken into consideration. Accordingly, when the miniaturized sizes and the power voltage have already been set, it is often required to lower the amount of an electric current flowing in the transistor. To lower the electric current in amount, provision is often made such that the gate oxide layer is thickened to lower the drive ability of the transistor. When such provision is made, the LSI is lowered in operational speed. This results in failure to make a high-speed LSI chip.
It is therefore required to provide a method of estimating, based on the actual operation of an LSI, the deterioration thereof due to hot carriers.